1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a redundancy circuit for remedying defective memory cells created during fabrication of a semiconductor memory device.
2. Description of the Related Art
In fabrication of semiconductor memory devices, it is very important to obtain a higher yield. Generally, if a fabricated semiconductor memory device has several defective memory cells, or even only one defective cell, it may be unusable as a memory device. Highly integrated semiconductor memory devices have many more defective memory cells than devices manufactured at a lower level of integration. Therefore, as the integration level of semiconductor memory devices increases, the increased number of defective cells causes the yield to fall.
The use of a redundancy circuit is a well-known technique for obtaining a desired yield rate when manufacturing semiconductor memory devices. A semiconductor device fabricated with this technique includes, in addition to a main memory cell array for storing binary data, a redundant memory cell array for replacing defective memory cells on in the rows/columns of the main memory with redundant memory cells. Redundant memory cells are connected to respective redundant word lines and bit lines. If fewer that several thousand defected memory cells are detected by testing the main memory cell array, they can be replaced with redundant memory cells. As a result, the memory chip can be fabricated as a non-defective article.
A redundant cell array which is arranged to replace defective memory cells on rows of the main memory cell array with redundant memory cells is called a row redundancy array. A redundant cell array which is arranged to replace defective cells on columns of the main memory cell array with redundant memory cells is called a column redundancy array. To replace the defective cells with the redundant cells, a redundancy circuit is required. A redundancy circuit includes: a circuit for storing location information for the defective cells, namely, repair addresses; a circuit for determining whether the repair addresses are identical with externally applied addresses; and the redundancy cell array.
A row redundancy circuit decodes row addresses received therein, and operates to replace defective regions with row regions corresponding to the redundant cell array when the row addresses are identical with the stored repair row addresses. Similarly, a column redundancy circuit operates to replace defective column regions of the main memory cell array with column regions corresponding to the redundant cell array by comparing the column addresses with the stored repair column addresses.
A redundancy decoder circuit stores repair addresses and determines whether row or column addresses are identical with the repair addresses. A redundancy decoder circuit has a row/column address buffer, a redundant row/column predecoder circuit, and a redundant row/column decoder circuit. The redundant row/column predecoder circuit has a plurality of redundant predecoders and the redundant row/column decoder circuit has a plurality of redundant decoders.
Each redundant row/column predecoder receives a row/column address signal RA0-RAi from the row/column address buffer and generates a redundancy enable signal for enabling the redundant decoders to be activated. The redundancy circuit is also activated by the redundancy enable signal. As well known in the art, the redundant decoder circuit in the row redundant circuit drives redundant word lines and the redundant circuit in the column redundant circuit drives column selection lines for selecting redundant bit line pairs.
Each of the redundant row/column predecoders has a plurality of fuses. In a semiconductor memory device with a redundant row/column predecoder, fuses are cut when there are defective cells that must be remedied.
As the integration level of semiconductor memory devices increases, the devices must be designed to operate with minimized active or standby power dissipation. However, in a semiconductor memory device with the above mentioned redundant predecoder, a constant amount of current (i.e., static current) always flows through the fuse during an active or standby state when a fuse is not cut. As a result, in a conventional semiconductor memory device, a constant amount of power is dissipated in relation to the operation characteristics of the redundancy circuit.